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august 2010 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 SG6741A ? highly integrated green-mode pwm controller SG6741A highly integrated green-mode pwm controller features ? high-voltage startup ? low operating current: 4ma ? linearly decreasing pwm frequency to 18khz ? frequency hopping to reduce emi emissions ? peak-current-mode control ? cycle-by-cycle current limiting ? leading-edge blanking (leb) ? synchronized slope compensation ? gate output maximum voltage clamp: 18v ? v dd over-voltage protection (auto restart) ? v dd under-voltage lockout (uvlo) ? internal open-loop protection ? constant power limit (full ac input range) applications general-purpose switch-mode power supplies and flyback power converters, including: ? power adapters ? open-frame smps description the highly integrated SG6741A series of pwm controllers provides several features to enhance the performance of flyback converters. to minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. to avoid acoustic-noise problems, the minimum pwm frequency is set above 18khz. this green-mode function enables the power supply to meet international power conservation requirements. with the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. to further reduce power consumption, SG6741A is manufactured using the bicmos process, which allows an operating current of only 4ma. SG6741A integrates a frequency-hopping function internally to reduce emi emission of a power supply with minimum line filters. a built-in synchronized slope compensation achieves stable peak-current-mode control. the proprietary internal line compensation ensures constant output power limit over a wide ac input voltages, from 90v ac to 264 v ac . SG6741A provides many protection functions. in addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. pwm output is disabled until v dd drops below the uvlo lower limit, when the controller starts up again. as long as v dd exceeds ~26v, the internal ovp circuit is triggered. SG6741A is available in an 8-pin sop package. ordering information part number operating temperature range package packing method SG6741Asy -40 to +105c 8-lead small outline package (sop) tape & reel
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 2 SG6741A ? highly integrated green-mode pwm controller application diagram figure 1. typical application block diagram figure 2. block diagram osc generator
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 3 SG6741A ? highly integrated green-mode pwm controller marking information figure 3. top mark pin configuration figure 4. pin configuration pin definitions pin # name description 1 gnd ground. 2 fb feedback. the signal from the external compensati on circuit is fed into this pin. the pwm duty cycle is determined in response to the signal on this pin and the current-sense signal on sense pin. 3 nc no connection. 4 hv startup input. for startup, this pin is pulled hi gh to the line input or bulk capacitor via resistors. 5 ri reference setting. a resistor connected from the ri pin to gnd pin provides a constant current source, which determines the center pwm fr equency. increasing the resistance reduces pwm frequency. using a 26k ? resistor for r i results in a 65khz center pwm frequency. 6 sense current sense. the sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 7 vdd power supply. the internal protection ci rcuit disables pwm output as long as v dd exceeds the ovp trigger point. 8 gate driver output. totem-pole output driver. so ft driving waveform is im plemented for improved emi. hv nc gate vdd sense ri gnd fb zxytt 6741a tpm f: fairchild logo z: plant code x: 1-digit year code y: 1-digit week code tt: 2-digit die run code t: package type (s = sop) p: y=green package m: manufacture flow code
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 4 SG6741A ? highly integrated green-mode pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. all voltage values, except differential voltages, are given with respect to the ground pin. symbol parameter min. max. unit v vdd dc supply voltage (1, 2) 30 v v fb fb pin input voltage -0.3 7.0 v v sense sense pin input voltage -0.3 7.0 v v ri ri pin input voltage -0.3 7.0 v v hv hv pin input voltage 500 v p d power dissipation (t a 50c) 400 mw ja thermal resistance (junction-to-air) 141 c/w t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or ir, 10 seconds) +260 c esd electrostatic discharge capability human body model, jesd22-a114, all pins except hv pin 4 kv machine model, jesd22-a115, all pins except hv pin 200 v notes : 1. all voltage values, except differential voltages, ar e given with respect to the network ground terminal. 2. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 5 SG6741A ? highly integrated green-mode pwm controller electrical characteristics v dd =15v; t a =25c, unless otherwise noted. symbol parameter conditions min. typ. max. units v dd section v dd-op continuously operating voltage 22 v v dd-on start threshold voltage 15.5 16.5 17.5 v v dd-off minimum operating voltage 9.5 10.5 11.5 v i dd-st startup current v dd-on ? 0.16v 30 a i dd-op operating supply current v dd =15v, gate open 4 5 ma i dd-olp internal sink current v dd-olp +0.1v 50 70 90 a v dd-olp i dd-olp off voltage 6.5 7.5 8.0 v v dd-ovp v dd over-voltage protection auto restart 25 26 27 v t d-vddovp v dd over-voltage protection debounce time auto restart 100 180 260 s hv electrical characteristics i hv supply current drawn from hv pin v ac =90v, (v dc =120v) v dd =10f 2 ma i hv-lc leakage current after startup hv=500v, v dd =v dd- off +1v 1 20 a oscillator section f osc frequency in nominal mode center frequency 62 65 68 khz hopping range 3.7 4.2 4.7 t hop hopping period 4.4 ms f osc-g green-mode frequency 16 18 21 khz f dv frequency variation vs. v dd deviation v dd =11v to 22v 5 % f dt frequency variation vs. temperature deviation t a =-20 to 85 c 5 % feedback input section a v input voltage to current-sense attenuation 1/3.75 1/3.20 1/2.75 v/v z fb input impedance 4 7 k ? v fb-open fb output high voltage fb pin open 5.5 v v fb-olp fb open-loop trigger level 3.7 4.0 4.3 v t d-olp the delay time of fb pin open- loop protection r i =26k ? 50 56 62 ms v fb-n green-mode entry fb voltage 1.9 2.1 2.3 v v fb-g green-mode ending fb voltage v fb-n - 0.5 v v fb-zdc zero duty-cycle input voltage 1 v continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 6 SG6741A ? highly integrated green-mode pwm controller electrical characteristics (continued) v dd =15v; t a =25c, unless otherwise noted. osc f f osc - v fb-g v fb-zdc v fb v fb-n pwm frequency figure 5. pwm frequency symbol parameter conditions min. typ. max. units current sense section z sense input impedance 12 k ? v sthfl current limit flatten threshold voltage 0.87 0.90 0.93 v v sthva current limit valley threshold voltage v sthfl ?v sthva 0.18 0.22 0.26 v t pd delay to output 100 200 ns t leb leading-edge blanking time 275 350 425 ns gate section dcy max maximum duty cycle 60 65 70 % v gate-l gate low voltage v dd =15v, i o =50ma 1.5 v v gate-h gate high voltage v dd =12.5v, i o =-50ma 8 v tr gate rising time v dd =15v, c l =1nf 150 250 350 ns tf gate falling time v dd =15v, c l =1nf 30 50 90 ns i gate-source gate source current v dd =15v, gate=6v 250 ma v gate-clamp gate output clamping voltage v dd =22v 18 v dcy max maximum duty cycle 60 65 70 %
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 7 SG6741A ? highly integrated green-mode pwm controller typical performance characteristics 0 5 10 15 20 25 -40 -25 -10 5 20 35 50 65 80 95 110 125 tem p erature ( c ) i dd -st (a) 0.0 1.0 2.0 3.0 4.0 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( c ) i dd -op ( m a ) figure 6. startup current (i dd-st ) vs. temperature figure 7. operating supply current (i dd-op ) vs. temperature 15.0 16.0 17.0 18.0 19.0 20.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( ) v dd -on (v) c 8.0 9.0 10.0 11.0 12.0 13.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 te m p erature ( c ) v dd -off (v) figure 8. start threshold voltage (v dd-on ) vs. temperature figure 9. minimum operating voltage (v dd-off ) vs. temperature 0.0 1.0 2.0 3.0 4.0 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c ) i hv (ma) 0 2 4 6 8 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( c ) i hv-lc (a) figure 10. supply current drawn from hv pin (i hv ) vs. temperature figure 11. leakage current after startup (i hv_lc ) vs. temperature 60 62 64 66 68 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( c ) f osc (khz) 60.0 62.0 64.0 66.0 68.0 70.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c ) dc y max ( % ) figure 12. frequency in nominal mode (f osc ) vs. temperature figure 13. maximum duty cycle (dcy max ) vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 8 SG6741A ? highly integrated green-mode pwm controller functional description startup current for startup, the hv pin is connected to the line input or bulk capacitor through an external resistor, r hv , which is recommended as 100k ? . typical startup current drawn from pin hv is 2ma and charges the hold-up capacitor through the resistor r hv . when the v dd capacitor level reaches v dd-on , the startup current switches off. at this moment, the v dd capacitor only supplies the SG6741A to maintain v dd before the auxiliary winding of the main transformer provides the operating current. operating current operating current is around 4ma. the low operating current enables a better efficiency and reduces the requirement of v dd hold-up capacitance . green-mode operation the proprietary green-mode function provides an off- time modulation to reduce the switching frequency in the light-load and no-load conditions. the on-time is limited for better abnormal or brownout protection. v fb , which is derived from the voltage feedback loop, is taken as the reference. once v fb is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency around 18khz (r i =26k ? ). oscillator operation a resistor connected from the ri pin to the gnd pin generates a constant current source for the controller. this current is used to determine the center pwm frequency. increasing the resistance reduces pwm frequency. using a 26k ? resistor r i results in a corresponding 65khz pwm frequency. the relationship between r i and the switching frequency is: (khz) ) (k i r 1690 pwm f = (1) the range of the pwm oscillation frequency is designed as 47khz ~ 109khz. current sensing and pwm current limiting peak-current-mode control is utilized in SG6741A to regulate output voltage and provide pulse-by-pulse current limiting. the switch current is detected by a sense resistor into the sense pin. the pwm duty cycle is determined by this current sense signal and v fb , the feedback voltage. when the voltage on the sense pin reaches around v comp = (v fb ?1.2)/3.2, a switch cycle terminates immediately. v comp is internally clamped to a variable voltage around 0.85v for output power limit. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs on the sense-resistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. du ring this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 16.5v and 10.5v. during startup, the hold-up capacitor must be charged to 16.5v through the startup resistor to enable the ic. the hold-up capacitor continues to supply v dd before the energy can be delivered from auxiliary winding of the main transformer. v dd must not drop below 10.5v during startup. this uvlo hysteresis window ensures that hold-up capacitor is adequate to supply v dd during startup. gate output / soft driving the bicmos output stage is a fast totem-pole gate driver. cross conduction is avoided to minimize heat dissipation, increase effici ency, and enhance reliability. the output driver is clamped by an internal 18v zener diode to protect power mosfet transistors against undesirable gate over voltage. a soft driving waveform is implemented to minimize emi. built-in slope compensation the sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. built-in slope compensation improves stability or prevents sub-harmonic oscillation. SG6741A inserts a synchronized positive-going ramp at every switching cycle. constant output power limit when the sense voltage, across the sense resistor r s , reaches the threshold voltage, around 0.9v, the output gate drive is turned off after a small delay, t pd . this delay introduces an additional current proportional to t pd ? v in / l p . since the delay is nearly constant, regardless of the input voltage v in, higher input voltage results in a larger additional current and the output power limit is higher than that under low input line voltage. to compensate this variation for wide ac input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. the power limiter is designed as a positive ramp signal fed to the inverting input of the ocp comparator. this results in a lower current limit at high-line inputs than at low-line inputs.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 9 SG6741A ? highly integrated green-mode pwm controller v dd over-voltage protection (ovp) v dd over-voltage protection has been built in to prevent damage due to abnormal conditions. once the v dd voltage is over the v dd over-voltage protection voltage (v dd-ovp ) and lasts for t d-vddovp , the pwm pulses are disabled until the v dd voltage drops below the uvlo, then starts again. over-vol tage conditions are usually caused by open feedback loops. limited power control the fb voltage increases every time the output of the power supply is shorted or overloaded. if the fb voltage remains higher than a built-in threshold for longer than t d-olp , pwm output is turned off. as pwm output is turned off, the supply voltage v dd begins decreasing. when v dd goes below the turn-off threshold (~10.5v) the controller is totally shut down. v dd is charged up to the turn-on threshold voltage of 16v through the startup resistor until pwm output is restarted. this protection feature continues as long as the overloading condition persists. this prevents the power supply from overheating due to ov erloading conditions. noise immunity noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. slope compensation helps alleviate this problem. good placement and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components near the SG6741A, and increasing the power mos gate resistance improve performance.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 10 SG6741A ? highly integrated green-mode pwm controller reference circuit 1 2 3 cn1 cn1 c2 2 1 + c4 2 1 3 4 bd1 2 1 d2 1 2 3 q2 r7 gnd 1 fb 2 nc 3 hv 4 ri 5 sense 6 vdd 7 gate 8 u1 SG6741A r4 1 2 4 3 u2 c6 r2 1 3 2 q1 2 1 + c7 2 1 d3 r9 r11 r10 r8 c11 2 1 + c9 vz1 c1 1 2 3 4 t1 4 2 3 7 8 6 5 t2 vo+ vo- c3 1 2 3 4 l1 2 1 + c8 1 2 3 4 l2 2 1 d1 a k r u3 vo+ 1 2 l4 r3 vo+ r1 c5 r6 c10 r5 c12 figure 14. circuit (12v/5a) bom reference component reference component bd1 bd 4a/600v q2 mos 7a/600v c1 xc 0.68f/300v r1 r 100k 1/2w c2 xc 0.1f/300v r2 r 47 1/4w c3 yc 222pf/y1 r3 r 100k 1/2w c4 ec 120f/400v r4 r 20 1/8w c5 cc 0.01f/500v r5 r 100 1/8w c6 cc 102pf/100v r6 r 33k 1/8w c7 ec 1000f/25v r7 r 0.3 2w c8 ec 470f/25v r8 r 680 m 1/8w c9 ec 22f/50v r9 r 4.7k 1/8w c10 cc 470pf/50v r10 r 150k m 1/8w c11 cc 222pf/50v r11 r 39k 1/8w c12 cc 103pf/50v t1 10mh d1 zener diode 15v 1/2w (option) t2 600h(pq2620) d2 byv95c u1 ic SG6741A d3 fr103 u2 ic pc817 f1 fuse 4a/250v u3 ic tl431 l1 900h vz1 vz 9g q1 stp20-100ct
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 11 SG6741A ? highly integrated green-mode pwm controller physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 15. 8-lead small outline package (sop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com SG6741A ? rev. 1.0.2 12 SG6741A ? highly integrated green-mode pwm controller

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